Novel Instructions and Their Hardware Architecture for Video Signal Processing

Abstract

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced by about 20/spl sim/25%. This paper also proposes new instructions for the integer transform. The proposed instructions can execute the 1D forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.