A 0.5V 2.2pW 2-transistor voltage reference

Abstract

A voltage reference using a depletion-mode device is designed in a 0.13 mum CMOS process and achieves ultra-low power consumption and sub-1V operation without sacrificing temperature and supply voltage insensitivity. Measurements show a temperature coefficient of 19.4 ppm/degC (3.4 muV/degC), line sensitivity of 0.033%/V, power supply rejection ratio of -67 dB, and power consumption of 2.2 pW. It requires only two devices and functions down to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> = 0.5 V with an area of 1350 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A variant for higher V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> is also demonstrated.