A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications

Abstract

A novel digitally-controlled oscillator (DCO) architecture for multi-GHz RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering. This enables use of fully-digital frequency synthesizers in the most advanced deep-submicron digital CMOS processes which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end on to a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a DSP. The DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset.