Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies

TLDR

3‑D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor, but increased device density and asymmetrical packaging make power delivery design challenging. We investigate various methods to improve 3‑D power delivery, providing the first detailed architectural‑level analysis. We analyze the impact of TSV size and spacing, C4 spacing, and dedicated power delivery TSVs—including coaxial TSVs—using a 3‑D evaluation system comprising a quad‑core chip multiprocessor, memory die, and accelerator engine evaluated with SPEC benchmark traces. Our results give clear guidelines for 3‑D power delivery and show that 2‑D‑like or better power quality can be achieved by increasing C4 granularity and selecting suitable TSV size and spacing.

Abstract

3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and spacing, of controlled collapse chip connection (C4) spacing, and of dedicated power delivery TSVs. In addition to considering typical cylindrical or square metal-filled TSVs (core TSVs), we also investigate using coaxial TSVs for power delivery resulting in reduced routing blockages and added coupling capacitance. Our 3-D evaluation system is composed of a quad-core chip multiprocessor, a memory die, and an accelerator engine, and it is evaluated using representative SPEC benchmark traces. This is the first detailed architectural-level analysis for 3-D power delivery. Our findings provide clear guidelines for 3-D power delivery design. More importantly, we show that it is possible to achieve 2-D-like, or even better, power quality by increasing C4 granularity and by selecting suitable TSV size and spacing.