Design of VLSI CMOS circuits under thermal constraint

Abstract

As process technologies continue to scale, the effects of temperature can no longer be neglected. High on-chip temperature causes frequency degradation, increases wasteful leakage power, and lowers device reliability. Therefore, managing on-chip temperature becomes an important design undertaking. In this brief, the effects of temperature on very large-scale integration design are presented, and an analytical technique is introduced to systematically design and evaluate thermal control mechanisms, such as the dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS). Using the energy-delay product (EDP) metric, the DFS is shown to outperform the DCT.