Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine

Abstract

This work deals with some performance aspects of the implementation of an algorithm to simulate MOS electronic circuits, modeled at the transistor level. The target architecture is a special purpose logic simulation machine, the Yorktown Simulation Engine (YSE), which has no direct support for loop mechanisms or conditional flow control. Since the simulation algorithm requires such mechanisms to determine whether and when a circuit reaches a steady state, we must calculate prior to simulation time, the number of iterations required for the algorithm to converge. We show how to arrange the order in which transistors are processed, aiming at a reduced number of such iterations, and therefore, an improved simulation performance. The results presented here show the optimal way to deal with acyclic circuits and some heuristic criteria to handle cyclic circuits. Also, we show a method to calculate the number of iterations required for the convergence of the simulation algorithm. These methods, originally developed for the YSE, have been also incorporated in a switch level simulator running on an IBM/370 architecture.