Drain-Bias Dependence of Threshold Voltage Stability of Amorphous Silicon TFTs

Abstract

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V/sub T/) stability performance. At small gate stress voltages (0/spl les/V/sub ST//spl les/15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V/sub T/(/spl Delta/V/sub T/) compared to the /spl Delta/V/sub T/ in the absence of a drain bias. The measured shift in V/sub T/ appears to agree with the defect pool model that the /spl Delta/V/sub T/ is proportional to the number of induced carriers in the a-Si:H channel.