Efficient generation of pre-silicon MOS model parameters for early circuit design

Abstract

The technology development cycle continues to shrink, which very often requires evaluation of circuit design and technology choices using circuit simulators at the time when no real silicon is available. In this paper, we present an efficient methodology for generating pre-silicon device models for advanced CMOS processes. The methodology allows accurate prediction of the full MOS I-V characteristics for the future technologies combining a constraint backpropagation algorithm based upon a few critical specifications, physical models for the advanced device phenomena, and the empirical data from devices of an existing technology. The methodology has been tested on two CMOS production technologies. Good prediction results are achieved: for nMOS the rms error is 1%-2%, for pMOS it is 2%-4%.