Design and optimization of multithreshold cmos (mtcmos) circuits

TLDR

Reducing power dissipation, especially subthreshold leakage that grows with scaling, is a critical challenge in VLSI, and multithreshold technology offers a promising solution. The study proposes heuristic gate‑clustering methods for multithreshold CMOS circuits, using bin‑packing and set‑partitioning models, and develops four hybrid techniques that combine these approaches. The authors formulate the clustering as a bin‑packing/set‑partitioning optimization that incorporates routing complexity and ground‑bounce constraints, and then devise hybrid algorithms that merge the two models. On six benchmarks, the proposed methods achieve on average 84 % leakage and 12 % dynamic power savings, while the hybrid solutions yield 72 % leakage and 9 % dynamic savings at adequate speeds and noise margins.

Abstract

Reducing power dissipation is one of the most important issues in very large scale integration design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multithreshold technology has emerged as a promising technique to reduce leakage power. This paper presents several heuristic techniques for efficient gate clustering in multithreshold CMOS circuits by modeling the problem via bin-packing (BP) and set-partitioning (SP) techniques. The SP technique takes the circuit's routing complexity into consideration which is critical for deep submicron (DSM) implementations. By applying the techniques to six benchmarks to verify functionality, results obtained indicate that our proposed techniques can achieve on average 84% savings for leakage power and 12% savings for dynamic power. Furthermore, four hybrid clustering techniques that combine the BP and SP techniques to produce a more efficient solution are also devised. Ground bounce was also taken as a design parameter in the optimization problem. While accounting for noise, the proposed hybrid solution achieves on average 9% savings for dynamic power and 72% savings for leakage power dissipation at sufficient speeds and adequate noise margins.