2005 · 59 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsVlsi DesignAnalog IntegrationClock Distribution NetworksClock ManagementCmos Circuit DesignI/o ArchitectureMixed-signal Integrated Circuit DesignCmos Analog Integrated CircuitsHigh-speed Circuit DesignHigh-speed Cmos DesignHigh-speed I/o Circuit DesignJitterJitter MeasurementReceiver SensitivityReceiver Sensitivity Analysis
A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of /spl plusmn/12mV at 6.4Gbit/s with BER <10/sup -14/ measured using 7b PRBS data.
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The design and implementation of a first-generation CELL processor
D. Pham, S. Asano, M. Bolliger et al. · 2005 · 547 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
K.-Y.K. Chang, J. Wei, S. Li et al. · 2003 · 21 citations
A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology
P. Landman, Ah-Lyan Yee, Runqi Gu et al. · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 20 citations
Engineering, Computer Engineering, Electrical Engineering +13