T. Chin

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

Haechang Lee, Kun-Yung Ken Chang, Jung‐Hoon Chun et al. · IEEE Journal of Solid-State Circuits · 2009 · 61 citations

Engineering, Computer Engineering, Electrical Engineering +13

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

Ken Chang, Sudhakar Pamarti, Kambiz Kaviani et al. · 2005 · 59 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Kambiz Kaviani, Ting Wu, J. Wei et al. · IEEE Journal of Solid-State Circuits · 2012 · 39 citations

Engineering, Computer Engineering, Electrical Engineering +11

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Amir Amirkhany, J. Wei, N. Mishra et al. · IEEE Journal of Solid-State Circuits · 2012 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17

Clocking circuits for a 16Gb/s memory interface

Ting Wu, Xudong Shi, Kambiz Kaviani et al. · 2008 · 19 citations

Engineering, Electrical Engineering, Analog Electronics +16