SRAM leakage suppression by minimizing standby supply voltage

Abstract

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V/sub DD/) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the basis for further design space explorations. This model is verified using simulations as well as measurements from a 4 kB SRAM chip in a 0.13 /spl mu/m technology. It is demonstrated that an SRAM cell state can be preserved at sub-300 mV standby VDD, with more than 90% leakage power savings.