Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips

Abstract

The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimensions, the increase of atomic fluctuations and the massive occurrence of physical defects. We focus on fault tolerance at the architectural level, and especially on fault-tolerance approaches, which are based on chip self-diagnosis and self-reconfiguration. We study test and reconfiguration methodologies in massively defective nanoscale devices, either at fine granularity field programmable devices or at coarse granularity multi-core arrays. In particular, we address the important question of up to which point could future chips have self-organizing fault-tolerance mechanisms to autonomously ensure their own dependable operation. In the case of FPGAs, we present known fault tolerant approaches and discuss their limitations in future nanoscale devices. In the case of multicore arrays, we show that such properties as self-diagnosis, self-isolation of faulty elements and self-reorganization of communication routes are possible.