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Evaluation of the SPUR Lisp architecture
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1986
Year
EngineeringComputer ArchitectureSoftware EngineeringSpur MicroprocessorProcessor ArchitectureSoftware AnalysisHardware ArchitectureHardware SecurityLisp ProgramsHigh-performance ArchitectureParallel ComputingInstruction-level ParallelismRisc-vComputer EngineeringComputer ScienceSoftware DesignCommon Lisp ProgramsEmbedded Operating SystemProgram AnalysisParallel ProgrammingIntermediate RepresentationSystem SoftwareSpur Lisp Architecture
The SPUR microprocessor has a 40-bit tagged architecture designed to improve its performance for Lisp programs. Although SPUR includes just a small set of enhancements to the Berkeley RISC-II architecture, simulation results show that with a 150-ns cycle time SPUR will run Common Lisp programs at least as fast as a Symbolies 3600 or a DEC VAX 8600. This paper explains SPUR's instruction set architecture and provides measurements of how certain components of the architecture perform.