Efficient Implementations for AES Encryption and Decryption

Lecture Notes in Computer Science 1205

Industrial Robot the international journal of robotics research and application · 1999 · 38.7K citations

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High-speed VLSI architectures for the AES algorithm

Xinmiao Zhang, Keshab K. Parhi · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 443 citations

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A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA

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Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors

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Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Gaël Rouvroy, François‐Xavier Standaert, J.-J. Quisquater et al. · 2004 · 159 citations · Full text

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