A low-power SRAM using improved charge transfer sense amplifiers and a dual-Vth CMOS circuit scheme

Abstract

In this paper we propose an improved version of the charge transfer sense amplifier (CT sense amp) which completely compensates the threshold voltage (Vth) difference of MOSFETs. We also present a dual-Vth CMOS circuit scheme that enables high speed operation and low leakage power consumption at low supply voltage. A low-power, low-voltage 2 k/spl times/16 b SRAM macro was designed and fabricated using a 0.25 /spl mu/m process. It showed stable operation with an access time of 7.0 ns and power consumption of 3.9 mW at 1.0 V (boost 1.5 V), 100 MHz, 85/spl deg/C.