2009 · 46 citations · 7 references
EngineeringComputer EngineeringComputer SystemsHardware-software Co-designLow-power DesignVirtualizationNetwork Performance AnalysisNetwork-on-chip DesignPerformance ModelingPerformance OptimizationPower ManagementPower-aware DesignEnergy ProfilingHardware Performance ModelingNetwork Performance OptimizationPower ConsumptionPower Consumption ModelingPower Consumption OptimizationPower-efficient ArchitectureThroughput
We consider a new generation of COTS software routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR networking performance and behavior. To this purpose, we separately characterized the roles of both HW and SW layers through a large set of internal and external experimental measurements, obtained with a heterogeneous set of HW platforms and SR setups. Starting from this detailed measure analysis, we propose a simple model, able to represent the SR performance with a high accuracy level in terms of packet throughput and related power consumption. The proposed model can be effectively applied inside "green optimization" mechanisms in order to minimize power consumption, while maintaining a certain SR performance target.
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Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen et al. · 2002 · 59 citations
Raffaele Bolla, Roberto Bruschi · 2008 · 58 citations · Full text