2010 · 16 citations · 13 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault ToleranceFault-tolerant ComputingError DetectionFault Tolerance DesignHardware Fault ToleranceReconfiguration After FailureRun-time ReconfigurationSoftware Fault ToleranceFault-tolerant ArchitectureFault-tolerant ReconfigurationPermanent FaultsProcessor ArchitectureProcessor FaultsSelf-repairSelf-testVliw Architecture
This paper describes a purely software-based approach to handle permanent faults in the data path of a statically scheduled superscalar processor architecture; e.g. a VLIW processor. This approach does not need any hardware in the processor core itself to reconfigure the data path. Rather the reconfiguration is done in software by modifying the binary code in the program memory of the processor. By this, the usage of a faulty component in the data path can be avoided during the execution of the program. The modification of the program is carried out by a repair routine that is executed by the faulty processor itself. It is shown that this is possible even if there is a fault in the data path. The modification of the binary code takes place immediately after a software-based self-test. Both, the self-test and the modification are carried out immediately after the start-up of the system. Thus, the detection and repair of a fault can happen in the field. Furthermore, the compiler must generate the program in a special way in order to guarantee that the binary code can be modified under all specified fault situations. A simple scheduling algorithm that produces such fault-tolerant binary code is presented, too.
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Reconfigurable architecture for autonomous self-repair
Subhasish Mitra, Wei-Je Huang, N.R. Saxena et al. · IEEE Design & Test of Computers · 2004 · 109 citations
Defect tolerance at the end of the roadmap
Malvika Mishra, Seth Copen Goldstein · 2004 · 82 citations
Incorporating fault tolerance in superscalar processors
M. Franklin · 2002 · 26 citations