2011 · 25 citations · 2 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ReliabilityIntegrated Circuit DesignLeakage Power ReductionSemiconductor ReliabilityVery-large-scale Integration LayoutCmos ReliabilityCmos ScalingDevice OptimizationKeep-out Zone DesignLeakageThrough-silicon Via DesignThrough-silicon ViasYield Enhancement
A through-silicon-via (TSV) process is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. TSV leakage, yield, C-V flat-band shift, Cu contamination, and reliability are significantly improved via process optimization. The preferred TSV processing could relax TSV stress and minimize keep-out zone (KOZ). In this study, we also address the impact of multiple-TSVs additive stress impact, TSV signal coupling effect, and TSV depletion impact to assess the power-TSV plug cell in design practice.
2
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Uksong Kang, Hoeju Chung, Seongmoo Heo et al. · IEEE Journal of Solid-State Circuits · 2010 · 487 citations
Engineering, Computer Engineering, Electrical Engineering +15
Design and Fabrication of 3D Microprocessors
Patrick Morrow, Bryan Black, M. Kobrinsky et al. · MRS Proceedings · 2006 · 47 citations