An improved synthesis algorithm for multiplexor-based PGA's

Abstract

The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures. They present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit. One source of improvement is the use of if-then-else DAGs (directed acyclic graphs) as subject graphs along with BDDs (binary decision diagrams). An important contribution is a very fast algorithm which always gives a match for a function onto the basic block of the architecture, when one exists. Results obtained on a number of benchmark examples are given. >