2008 · 24 citations · 2 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignPower ManagementPower OptimizationAnalog-to-digital ConversionCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos Digital Circuit DesignEnergy-efficient Digital CircuitsLow-power Cmos DesignPower ConsumptionPower Consumption Optimization
An 8-bit 800MS/s time-interleaved pipeline ADC with SNDR of 47.8dB and 44.2dB for 1MHz and 400MHz inputs is presented. The techniques of Sub-ADC preamp sharing and reference voltage buffer current-reusing are proposed to minimize power consumption. The ADC implemented in 65nm digital CMOS process with an active area of 0.12mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> consumes 30mW from a 1.2V supply and achieves a FOM of 0.28pJ/conversion-step.
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A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS
Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin et al. · 2007 · 37 citations