The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

Abstract

Single-wire, synchronous clocking systems for increasingly large and complex microprocessors present major technical challenges: Die size increases whereas target clock skew and jitter typically remain a constant percentage of a decreasing cycle time. The clocking methodology of the present Alpha microprocessor handles such challenges by radically departing from a single chip-wide clock distribution, to better control clock skew, jitter and power dissipation. Four major clocks (one reference and three derived) are used to clock separate chip sections.