IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2010 · 65 citations · 16 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysLow-power DesignAccelerator ArchitectureField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationLow-power Digital Circuit DesignLow-power Fpga DesignArithmetic Logic Unit ArchitectureDiscrete Logarithm AlgorithmsDiscrete Logarithm ProblemFast Arithmetic CircuitsFinite-precision Arithmetic CircuitsFloating-point ArithmeticLinear Interpolation
A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that correct the piecewise interpolation error. The architecture has been implemented in an FPGA device and the results are compared with other low cost architectures requiring less area and achieving high-speed.
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