Layout aware design of mesh based NoC architectures

Abstract

Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system-level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.