IBM Journal of Research and Development · 1981 · 261 citations · 2 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsComputer ArchitectureData StructuresBoolean AlgebraLogic SynthesisLookup TablesAddersFast Arithmetic CircuitsTruth Table Specification
Based on the bit pair (a <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> , b <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> ) truth table, the carry propagate p <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> and carry generate g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> have dominated the carry-look-ahead formation process for more than two decades. This paper presents a new scheme in which the new carry propagation is examined by including the neighboring pairs (a <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> , b <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</inf> ; a <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i+1</inf> , b <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i+1</inf> ). This schem e not only reduces the component count in design, but also requires fewer logic levels in adder implementation. In addition, this new algorithm offers an astonishingly uniform loading in fan-in and fan-out nesting.
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Conditional-Sum Addition Logic
Jack Sklansky · IEEE Transactions on Electronic Computers · 1960 · 567 citations
High Speed Binary Parallel Adder
IEEE Transactions on Electronic Computers · 1966 · 24 citations