Publication | Closed Access
An efficient microcode compiler for application specific DSP processors
86
Citations
22
References
1990
Year
Efficient Microcode CompilerEngineeringCompiler TechnologyComputer ArchitectureSystem-level DesignEmbedded SystemsProcessor ArchitectureHardware SystemsComputer DesignCompilersParallel ComputingInstruction-level ParallelismCompiler SupportComputer EngineeringHardware OptimizationLoop FoldingComputer ScienceOptimizing CompilerProgram AnalysisMicrocode CompilationParallel ProgrammingProcessor Architectures
A computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques to solve these problems are developed. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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