Impact of three-dimensional architectures on interconnects in gigascale integration

TLDR

Three‑dimensional architectures can shorten the longest interconnects, though varying strata separation mainly affects the number of interstratal connections rather than their length. The authors present an interconnect distribution model for homogeneous 3‑D architectures with variable strata separation. The model is developed within a multilevel interconnect framework for homogeneous 3‑D architectures. For an ITRS 2005 100 nm ASIC, the two‑strata design yields a 3.9× increase in wire‑limited clock frequency, an 84 % reduction in wire‑limited area, and a 25 % decrease in required metal levels. Realizing these benefits requires fabrication advances such as improved alignment tolerances in wafer‑bonding techniques.

Abstract

An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9/spl times/ increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits.