Publication | Closed Access
Asynchronous Sequential Switching Circuits with Unrestricted Input Changes
62
Citations
5
References
1971
Year
Interval δ2EngineeringUnrestricted Input ChangesRow AssignmentBinary Input SignalsTest EngineeringCircuit SystemTiming AnalysisClocked CircuitsTimed SystemAsynchronous Vlsi DesignCircuit SynthesisAsynchronous CircuitsTime Delay SystemSynchronous DesignComputer EngineeringComputer ScienceSignal ProcessingCircuit DesignFormal MethodsDigital Circuit DesignAsynchronous SystemsMulti-chip Interconnects
Designing asynchronous circuits with independent input changes is challenging because closely spaced changes are treated as simultaneous, widely spaced changes as sequential, and intermediate spacing can cause unsatisfactory behavior. The study derives constraints on row assignment and delay elements to address these timing issues.
The problem of designing asynchronous circuits where the changes in binary input signals occur independently of one another is discussed. If several input changes occur within some interval δ1, the circuit behaves as though the changes were simultaneous. If consecutive changes are spaced by intervals exceeding some longer interval δ2 then the circuit reacts as though a sequence of single changes had occurred. But when the spacing is between these values, the system may react in an unsatisfactory manner unless special attention is paid to the problem during the design process. Constraints imposed by this problem on the row assignment and on the delay elements are derived.
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