Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing

Abstract

We have experimentally established that the inverse subthreshold slope <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -values below 60 mV/dec for optimized device structures.