A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric - Concepedia

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A low-power RISC microprocessor using dual PLLs in a 0.13 μm SOI technology with copper interconnect and low-k BEOL dielectric

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Citations

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References

2003

Year

D. Appenzeller, E. Cohen, Serge A. Charlebois, P. Kartschoke, P. McCormick, Norman J. Rohrer, G. Salem, Peter A. Sandon, Ben Singer, T. Von Reyn,

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

EngineeringVlsi DesignComputer ArchitecturePower ElectronicsInterconnect (Integrated Circuits)Electromagnetic CompatibilityLow-k Beol DielectricClock FrequenciesClock RecoveryLow-power Risc MicroprocessorElectronic PackagingMultiple PllsPower-aware DesignElectrical EngineeringEnergy HarvestingHigh-frequency DeviceComputer EngineeringMicroelectronicsFrequency ControlLow-power ElectronicsDynamic FrequencyVlsi ArchitectureDual Plls

Abstract

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.

References

	Year	Citations

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