2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 26 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDynamic Power ReductionIntegrated Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignTiming AnalysisBattery Life ManagementClock Network Power ReductionLow-power Circuit DesignLow-power Clock Network DesignLow-power Cmos DesignLow-power Interconnect DesignPower Reduction AnalysisUltra-low-power Cmos
Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.
3
CMOS technology: Present and future
B. Davari · 2003 · 23 citations
Engineering, Computer Engineering, Electrical Engineering +17