IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2006 · 23 citations · 14 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysHardware Description LanguagesChannel CodingCoding TheoryError Control CodingError-correcting CodesField-programmable Gate Array ArchitectureFpga ArchitectureApplication-specific Integrated Circuits (Asics)Convolutional CodesLdpc CodesLow-density Parity-check CodesParity Check CodesSequential Circuit SynthesisSequential DecodingTermination Sequences
Low-density parity-check convolutional codes (LDPC-CCs) complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice, video, and packet switching networks. In order to use these codes efficiently we must generate termination sequences similar to those used in conventional convolutional codes. In this paper, we present a construction method for termination sequence generation circuits suitable for field-programmable gate arrays and application-specific integrated circuits. This method uses linear algebra to determine the termination sequence for a small number of states of the encoder and converts these solutions into a sequential circuit. Results are presented for several realizations of termination circuits for a (128,3,6) LDPC-CC
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