IEEE Design & Test of Computers · 2005 · 69 citations · 6 references
EngineeringComputer EngineeringComputer ScienceHardware-software Co-designReconfigurable ComputingVirtualizationAccelerator ArchitectureHardware AccelerationHardware VirtualizationReconfigurable AcceleratorsReconfigurable System ArchitectureVirtualization ArchitectureAcceleratorsHardware ReconfigurationHardware-software IntegrationReconfigurable ArchitecturesReconfigurable Computing ArchitecturesReconfigurable Hardware ArchitectureReconfigurable MicroarchitectureSystem Virtualization
Reconfigurable‑system programmers and designers should develop algorithms and hardware accelerators independently of the underlying platform. The authors propose a portable, hardware‑agnostic programming paradigm that delegates platform‑specific tasks to a system‑level virtualization layer, introduces a multithreaded model based on a unified virtual‑memory image, and aims to achieve seamless hardware‑software interfacing and portability with minimal performance penalties. The system‑level virtualization layer supports a chosen programming model, hides platform details from users, and implements a multithreaded programming model using a unified virtual‑memory image for both software and hardware components.
Ideally, reconfigurable-system programmers and designers should code algorithms and write hardware accelerators independently of the underlying platform. To realize this scenario, the authors propose a portable, hardware-agnostic programming paradigm, which delegates platform-specific tasks to a system-level virtualization layer. This layer supports a chosen programming model and hides platform details from users much as general-purpose computers do. We introduce multithreaded programming model for reconfigurable computing based on a unified virtual-memory image for both software and hardware application parts. We also address the challenge of achieving seamless hardware-software interfacing and portability with minimal performance penalties.
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The MOLEN polymorphic processor
S. Vassiliadis, Stephan Wong, Georgi Gaydadjiev et al. · IEEE Transactions on Computers · 2004 · 393 citations · Full text
Programming models for hybrid FPGA-cpu computational components: a missing link
David Andrews, D. Niehaus, Razali Jidin et al. · IEEE Micro · 2004 · 118 citations