Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors

TLDR

Prior work on power‑aware thread‑level parallelism on CMPs has largely targeted multiprogrammed workloads, yet parallel execution of a single application remains essential for meeting future performance demands. This study seeks to dynamically optimize the power consumption of a parallel application running on a many‑core CMP while satisfying a specified performance constraint. The authors formulate a two‑dimensional optimization space over active core count and dynamic voltage/frequency scaling, and propose lightweight heuristics that drastically reduce search effort along both dimensions. Experiments on several parallel applications show that the optimal operating point varies with CMP characteristics, application behavior, and performance target, and that the heuristics rapidly converge to configurations that achieve near‑optimal power savings in almost all cases.

Abstract

Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single application is critical in light of the expanding performance demands of important future workloads. This work addresses the problem of dynamically optimizing power consumption of a parallel application that executes on a many-core CMP under a given performance constraint. The optimization space is two-dimensional, allowing changes in the number of active processors and applying dynamic voltage/frequency scaling. We demonstrate that the particular optimum operating point depends nontrivially on the power-performance characteristics of the CMP, the application's behavior, and the particular performance target. We present simple, low-overhead heuristics for dynamic optimization that significantly cut down on the search effort along both dimensions of the optimization space. In our evaluation of several parallel applications with different performance targets, these heuristics quickly lock on a configuration that yields optimal power savings in virtually all cases.