Stress induced leakage current and bulk oxide trapping: temperature evolution

Abstract

A key issue for flash cell scaling down is the reduction of tunnel oxide thickness. This is mainly limited by the information loss induced by the higher gate leakage current after cycling, becoming critical below 10 nm thickness. Multiple trap assisted tunneling has been proposed to model the conduction of degraded thick oxides, but it is not yet clear the nature of the associated defects. Data reported here are obtained on flat area capacitors with a standard full CMOS process with STI (shallow trench isolation) and dual-gate technology. Tunnel oxides of 8 nm thickness have been grown with different oxidation technologies. The measurement procedure is based on three steps to estimate the stable charge (Q/sub stable/), and its position, and the stationary SILC (stress induced leakage current) measured at a fixed field and extrapolated by the tunneling front model.