Formal verification of reconfigurable cores

Abstract

We show how a formal verification methodology can complement conventional verification for the development of FPGA-based cores. As FPGAs become larger, there is a greater reliance on shrink-wrapped intellectual property. In particular, customers expect rigorous verification of the cores that they purchase. We report on positive experience of using formal verification to facilitate the development of real cores. We then show how formal verification has a special role to play during the dynamic reconfiguration of cores.