Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

TLDR

MP‑SoC platforms are emerging, and power and wire constraints are driving modular, parallel design methodologies that rely on scalable communication fabrics such as networks‑on‑chip, whose trade‑offs span latency, throughput, energy, and silicon area. The authors aim to develop a consistent, meaningful evaluation methodology to compare the performance and characteristics of various NoC architectures. They evaluate design trade‑offs by comparing common NoC topologies, mapping a typical multiprocessing platform onto different interconnects, and illustrating how topology choices affect system performance. This work is the first comprehensive characterization of NoC architectures, showing how trade‑offs among latency, throughput, energy, and area differ across topologies and how these choices impact overall system performance.

Abstract

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.