A 0.02mm<sup>2</sup> 65nm CMOS 30MHz BW all-digital differential VCO-based ADC with 64dB SNDR

Abstract

A 300MHz all-digital differential VCO-based ADC occupies 0.02mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65nm CMOS, achieving a peak SFDR of 79dB and an SNDR of 64dB over a 30MHz BW. This high linearity is obtained using two VCOs in differential configuration in combination with an 11-points digital calibration. The power consumption is 11.4mW and the FOM is 150fJ/conv. step.