The design and implementation of the IMS A110 image and signal processor

Abstract

The IMS A110 provides a solution to many real-time image- and signal-processing problems by supporting techniques such as 1-D/2-D convolution/correlation statistical/histogram data collection and nonlinear data transformation. It is a cascadable, software configurable single-chip digital signal-processing device that operates at 20 MHz with a data throughput of 420 MOPS (million operations per second), and consists of three programmable length shift registers, a configurable 21-stage multiple-accumulate array (MAC), a postprocessing unit (PPU) and a microprocessor interface. The chip is fabricated in a single-level-metal 1.2-μm polysilicide CMOS process and contains around 375 K transistors on a 9.6-mm×8.1-mm die, which translates to a site density of 4.1 transistors/mil <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (excluding the pad ring). The authors present an overview of the A110 architecture and highlight the key design techniques used to implement the multiply accumulate array