An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

Abstract

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with plusmn2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N-1</sup> times 2pi linear range with N-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 mus logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is -48.7 dBc and the phase noise is -88.31dBc/Hz at 10 kHz offset with K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> = - 2 GHz/V.