Multi-step word-line control technology in hierarchical cell architecture for scaled-down high-density SRAMs

Abstract

A new hierarchical cell SRAM architecture, combined with a multi-step word-line control technology, has been developed to overcome rapid increase in random variability with no area-penalty. A 40nm-node 0.248 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -cell SRAM using a single power supply has been successfully fabricated, pushing up bit-density to 2.98Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .