IEEE Transactions on Computers · 1988 · 87 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureFault-tolerant ComputingVlsi DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingError Control CodingField-programmable Gate Array ArchitectureMixed-signal Integrated Circuit DesignErasure CorrectionPipelined Digital CircuitsReed-solomon CodesReed-solomon CodingSystolic Array DesignSystolic ArraysVery-large-scale Integration (Vlsi) DesignVlsi Implementation
A novel VLSI design for a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous study is replaced by a time-domain algorithm through a detailed comparison of their VLSI implementations. An architecture that implements the time-domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, an implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Some improvements result in both enhanced capability and significant reduction in silicon area, making it possible to build the decoder on a single chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A VLSI Design of a Pipeline Reed-Solomon Decoder
Shao, Truong, Deutsch et al. · IEEE Transactions on Computers · 1985 · 222 citations
Engineering, Computer Engineering, Electrical Engineering +16