A partitioning scheme for optimizing interconnect power

Abstract

An architecture-synthesis technique for the low-power implementation of real-time applications is presented. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexors and buffers, and more compact layouts. Experimental results show average reductions in bus and multiplexor power of 57.8 and 56.0%, respectively, resulting in an average reduction of 25.8% in total power. In addition, we analyze the effect of varying levels of partitioning on power consumption and present models for estimating bus capacitance.