A clock delayed sleep mode domino logic for wide dynamic OR gate

Abstract

A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide fan-in domino logic. The CDSM-domino logic not only improves the robustness but also reduces the active and stand-by power. The proposed scheme reduces delay by 21%, dynamic power by 16%, and leakage power by 91% respectively compared to the typical wide fan-in domino logic in 0.18? CMOS technology. In addition, the sleep mode entrance power is reduced to 10-5 of the HS-domino logic [3].