A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

Abstract

Time-interleaved architectures employ multiple signal processing paths in parallel to achieve high overall speed while maintaining relaxed speed requirements on individual channels. This type of architecture requires a precise multi-phase clock generator to implement the interleaving function with the performance of the system depending upon the uniformity of the clock signals. This work implements an on-chip dynamic skew calibration multi-phase clock generator with ultra-low jitter. This scheme does not require any additional calibration cycle and therefore does not interrupt the clock output at any time.