Source-drain breakdown in an insulated gate, field-effect transistor

Abstract

In IGFET operation, electrical breakdown between source and drain has been attributed to drain-junction avalanche breakdown. IGFET source-drain breakdown occurs at voltages less than drain-junction avalanche breakdown; this voltage decreases with decreasing channel length. Source-drain breakdown can be induced by increasing gate biasing voltage. Moreover, a large breakdown current is often sustained after removing the gate voltage. In this situations the IGFET "latches" in a source-drain breakdown mode. IGFET source-drain breakdown can be attributed to the extrinsic (or parasitic) bipolar transistor in parallel with the intrinsic IGFET structure. Carrier multiplication within the drain space-charge layer produces a substrate potential distribution that turns on this parasitic region; thus, IGFET source-drain breakdown is equivalent to emitter-collector breakdown (BV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEX</inf> ) for a bipolar transistor. Our mathematical model semi-quantitatively shows: the IGFET source-drain breakdown characteristics; the "latching"phenomenon; and the reduction of source drain breakdown voltage with decreasing channel length.