Publication | Closed Access
The Implementation of the 65nm Dual-Core 64b Merom Processor
59
Citations
2
References
2007
Year
Coretrade ArchitectureElectrical EngineeringManycore ProcessorEngineeringHigh-performance ArchitectureDual-core 64BComputer EngineeringComputer ArchitecturePmos PowerMany-core ArchitectureParallel ProgrammingComputer ScienceParallel ComputingMerom ProcessorMicroelectronicsProcessor Architecture
Merom is a dual-core 64b processor implementing the Coretrade architecture. The 143mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die has 291M transistors in a 65nm 8M process. The shared 4MB 16-way L2 cache uses PMOS power gating to minimize leakage. The processor operates in a wide core frequency range of 1 to 3GHz, a bus frequency range of 666 to 1333MHz and voltage range of 0.85 to 1.325V, while providing 40% better power performance.
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