System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit

Abstract

Considering the effects of thinned silicon dies and structures like TSVs and μ-bumps is essential for accurate thermal analysis of vertically integrated circuits. This paper presents an innovative compact thermal modeling approach for 3D ICs targeting system-level thermal analysis. This method uses material homogenization and formal reduction techniques for model simplification. It enables taking into account the microscopic structures required for 3D integration while keeping the model complexity affordable for fast simulations. A complete system including a packaged 65nm memory-on-logic circuit, socket and board has been modeled using the proposed thermal modeling approach. Power dissipation hot spots are emulated in the 3D circuit by using a set of resistive heaters while temperature is monitored using integrated thermal sensors. Simulation results from both steady-state and transient analyses show the thermal model is able to capture the hot spot effects with fast simulation times. Thermal data extracted from the 3D circuit demonstrate that simulation fits the thermal transient response and that steady-state analysis for various power profiles presents a worst case temperature error lower than 12% and an average error of 4.2%.