A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

Abstract

A 10b 205MS/S 1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> single-ended input at 205MS/S. The core ADC power consumption is 40mW from a 1V non-regulated supply.