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16×16 bit parallel multiplier based on 6 K gate array with 0.3 μm AlGaAs/GaAs quantum well transistors
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1992
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Electrical EngineeringEngineeringVlsi DesignBit Parallel MultiplierElectronic EngineeringApplied PhysicsComputer EngineeringAigaas/gaas QuantumμM Algaas/gaasIntegrated CircuitsK Gate ArrayMicroelectronicsBeyond CmosSemiconductor DeviceElectronic Circuit
The design and performance of a 16×16 bit parallel multiplier based on a 6 K gate array will be presented. This LSI semicustom IC demonstrates the high potential of our AIGaAs/GaAs quantum well FETs with a gate length of 0.3 μm. The best multiplication time measured was 7.2 ns.