A class of systolic serial-parallel multipliers

Abstract

A scheme for a fully-systolic bit-serial multiplier is presented, based on merging two adjacent cells of an existing semi-systolic multiplier in a single new cell. The multiplier has immediate response and high bit-throughput, limited by the propagation delay of one gated full adder and a latch. A way to increase the word-throughput, while retaining systolicity, is also presented.